1. Field of the Invention
The invention relates to a method of fabricating a capacitor of a dynamic random access memory (DRAM), and more particularly to a method of fabricating a capacitor over a bit line (COB) of a DRAM.
2. Description of the Related Art
DRAM is applied broadly in the field of integrated circuits devices, and more importantly, in the electronics industry. DRAMs with higher capacitance are necessary for the development of the industry; as a result, DRAMs with higher density and capacitance are of great interest and are developed by the related industry. How to keep the quality as the size of the device is reduced is now a task for the industry to overcome.
For the storage of digital data, the capacitance of the memory is called a "bit" and the unit for data storage in a memory is called a "memory cell". The memory cell is arranged in array, consisting of columns and rows. A set of a column and a row represents a specific address. Memory cells in the same column or the same row are coupled by a common wiring line, which is called a word line. The vertical wiring line related to data transmittance is called a bit line. The current design of DRAM is composed of a transistor, which is series-coupled to a capacitor to replace the original memory consisting of three transistors. In this manner, the circuit is simplified and the density of the device can be increased.
For the design of Ultra Large Scale Integration (ULSI) DRAM, the lithography and alignment controlling the contact is more and more critical as the device size reduces gradually.
FIG. 1 is a cross sectional view of the conventional COB of DRAM. A substrate 100 with a gate oxide layer 102 formed is provided. A polysilicon layer used as gates 104a, 104b and wiring line 104c is formed and a source/drain region 106a, 106b is then formed on the substrate 100. An insulating layer 108 is next formed to cover the gates 104a, 104b and wiring line 104c. A polysilicon layer is formed and then defined as bit lines 110a, 110b. A planarized oxide layer 112a, 112b is provided on the bit lines 110a, 110b and a contact hole is formed by defining and etching the oxide layer 112b, 112a and the insulating layer 108 to expose the source/drain region 106c. The contact hole is filled with a polysilicon layer 113 to serve as a lower electrode of the capacitor. A dielectric layer 114 is formed on the polysilicon layer 113 and a polysilicon layer 116 is formed on the dielectric layer 114. The polysilicon layer 116 serves as an upper electrode.
As shown in FIG. 1, the etching process becomes more difficult when the device size decreases in order to obey the design rule. The lower electrode 113, the gate 104b and the bit line 110a in FIG. 1 are isolated by insulating layer 108 and oxide layer 112a, 112b. In order to form the contact, the insulating layer 108 and the oxide layer 112a, 112b are etched while the contact hole is defined. The isolation between the lower electrode 113, the gate 104b and the bit lines 110a degrades as the cell size reduces and this affects the device reliability. Also, the difficulty of fabrication which is limited by lithography technology increases.